XDR DRAM

XDR DRAM is a high performance RAM with clocking in at 3.2GHz, providing up to 6.4 GB/sec bandwidth. The XDR solution was engineered to be effective in small high-bandwidth consumer systems as well as in high-performance main memory applications. Rambus owns the technology.

• Memory physical description
  • 1 to 16 bit native data bus widths
  • 8 bank memory architecture
  • Point-to-point data interconnect
  • CSP packaging

• Highest pin bandwidth
  • 3.2 to 6.4 GHz clockspeed
  • Octal Data Rate (ODR) signaling
  • Bi-directional differential RSL (DRSL)
  • Programmable on-chip termination
  • Adaptive impedance matching

• Highest sustained device bandwidth
  • 6.4 to 12.8 GB/sec sustained data rate for x16 data bus width device
  • Up to 4 Bank-interleaved transactions at full bandwidth
  • Dynamic request scheduling
  • Early-read-after-write support for maximum efficiency
  • Zero overhead refresh

• Low latency
  • 1.25/2.0/2.5/3.33 ns request packets

• Low power
  • 1.8V Vdd
  • Programmable ultra-low-voltage DRSL 200mV swing
  • Low-power PLL/DLL design
  • Power-down self-refresh support
  • Dynamic data width support with dynamic clock gating
  • Per pin I/O power-down
  • Sub-page activation support

• Ease in system design
  • Per bit FlexPhase circuits compensate to a 2.5ps resolution
  • XDR Interconnect uses minimum pin count