Application-specific integrated circuit

Overview

An ASIC (application-specific integrated circuit) is an integrated circuit (IC) customised for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. In contrast, a microprocessor is not, because users can adapt it to many purposes.

As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5000 gates to over 100 million. Modern ASICs often include entire 32-bit processors and other large building-blocks. Such an ASIC is often termed a SoC (System-on-a-chip). Designers of ASICs use a Hardware_description_language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.

For smaller designs and/or lower production volumes, ASICs have started to become a less attractive solution, as field-programmable gate arrays (FPGAs) grow larger, faster and more capable.

History

The initial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customisation occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customised by both metal and polysilicon layers. Some base dies include RAM elements.

Standard Cell ASIC Design

In the 1980s, logic synthesis tools, such as Design Compiler, became available. Such tools could compile HDL descriptions into to a gate-level netlist. This enabled a style of ASIC design called standard-cell design. Standard-cell ASICs are designed in the following conceptual stages, although these stages overlap significantly in practice.

1. A team of design engineers design team starts with a non-formal understanding of the required functions for a new ASIC, usually derived from Requirements analysis.
2. The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a computer program in a high-level language. This is usually called the RTL (Register transfer level) design.
3. Since the RTL design is quite complex, it is typically subjected to a range of verification tests, using simulation and/or Formal verification to ensure correctness.
4. A logic synthesis tool, such as Design Compiler, transforms the RTL design into a large collection of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consists of pre-characterized collections of gates (such as 2 input nor, 2 input nand, invertors, etc.). The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gate-level netlist.
5. The gate-level netlist is next processed by a place and route tool. The placement tool places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints. Computer methods such as simulated annealing are used to find a placement that meets all constraints, since the number of possible placements is too large to examine exhaustively.
6. The routing tool takes the physical placement of the standard cells and attempts to create the electrical connections between them. Since many signals must be routed, and since no two signals may “touch” each other, this process also locates a “sufficient” rather than “globally-optimal” solution. The output is a set of photomasks allowing a Semiconductor Fabrication effort to produce physical IC’s.

Full-Custom ASIC Design

Designers can also take the "full-custom" route in implementing an ASIC. In this case, an individual description of each transistor occurs in building the circuit. A "full-custom" implementation may function five times faster than a "standard-cell" implementation. The "standard-cell" implementation can usually be implemented quite a bit quicker and with less risk of errors, than the "full-custom" choice.

Structured ASIC Design

On the opposite side of the customization spectrum, a recent technology called "structured ASIC" emerged. In a "structured ASIC" design, the logic mask-layers of a device are predefined and are usually supplied by a third party. Design differentiation and customization is achieved by creating custom metal layers that create custom connections between predifined lower-layer logic elements. "Structured ASIC" technology is seen as bridging the gap between field-programmable gate arrays and "standard-cell" ASIC designs. Because only a small number of chip layers must be custom-produced, "structured ASIC" designs have much smaller non-recurring expenditures (NRE) than "standard-cell" or "full-custom" chips, which require that a full mask set be produced for every design.

IP-Based Design

The use of intellectual property blocks (IP-blocks) in ASICs has become a growing trend. These are designs intended to be sub-components of a larger ASIC. They may be provided as an HDL description (often termed a soft macro), or as a fully routed design that could be printed directly onto an ASIC’s mask (often termed a hard macro). Many organizations now sell such pre-designed IP, and larger organizations may have an entire department or division to produce such IP for the rest of the organization. For example, one can purchase CPUs, ethernet, USB or telephone interfaces.